As is well known, transistors in semiconductor devices are commonly constructed on silicon wafers using a chemical vapor deposition (CVD) process along with many other process steps. Individual transistor components are fabricated on a wafer using conventional deposition and etching techniques. Components are formed over either n-tub or p-tub regions in the silicon substrate. The individual transistor regions are then doped with either an n-type or p-type dopant according to the desired type of semiconductor device.
In p-channel metal oxide semiconductor (PMOS) devices, boron is typically the p+dopant that is implanted into the source/drain regions. However, during this phase of the manufacturing step, heavily doped boron in the polysilicon gate has a tendency to diffuse laterally around the gate or transversely through the gate and into the p-channel areas of the device. This diffusion often leads to severe threshold voltage instablilities and reliability problems in the PMOS device.
To minimize the diffusion of these dopants, a barrier layer is typically formed over the polysilicon gate. In many instances, the barrier layer may comprise a tungsten nitride, a tungsten silicide nitride or a titanium-nitride (TiN). The titanium-nitride has problems associated with its use because it oxidizes at ambient temperatures making it prone to oxidation problems. Furthermore, titanium-nitride cannot withstand the high temperatures of certain subsequent processing steps, such as source/drain annealing, which typically occurs around 900.degree. C. to 1000.degree. C.; thus, it cannot be used in deposition schemes in which these temperatures are encountered. While tungsten-based silicides can withstand high temperature anneals, a problem arises with their use when they are used with conventional gate deposition process, as explained below.
As the size of gate devices has reached the sub-micron range (i.e., 0.25 microns or less), the integrity of the junction or interface between the polysilicon gate structure and the silicide barrier layer has become an issue. In conventional processes, polysilicon or amorphous silicon is typically used to form the gate structure, which is subsequently overlayed with a metal-based barrier layer, such as tungsten nitride or tungsten slicide nitride. This barrier layer/gate structure formation is typically followed by a high temperature anneal of some type. During this anneal, the silicide integrity at the junction/interface between the polysilicon gate and the silicide barrier layer becomes corrupt, which often leads to leakage, and thus, penetration of the boron dopant through the gate structure and into the p-channel. This problem is even more acute where the gate structure is initially formed from amorphous silicon.
As well known, amorphous silicon re-crystallizes into polysilicon in the presence of annealing temperatures in excess of 500.degree. C. In such instances, re-crystallization can cause abnormal grain growth, which in turn, corrupts the silicide integrity and allows the dopant to penetrate into the p-channel.
Accordingly, what is needed in the art is a process that provides for a gate structure that can withstand annealing temperatures such that suppression of dopant penetration, both lateral and transverse, occurs with a simultaneous improvement of the silicide integrity.